In order to reduce the logic overhead caused by the full scan method in the FPGA-based fault injection attack emulation, this study proposes a partial scan based method for the simultaneous control of circuit states, i. e. , setting the values of all flip-flops in the circuit at any time, to emulate the fault injection attack. This emulation allows the early security assessment of integrated circuits during the design phase. Meanwhile, the method abstracts the circuit as a graph, extends the balanced-structure based partial scan method to select flip-flops, and then adds enable signals to achieve simultaneous control of all flip-flops. In addition, based on circuit logic, the SAT satisfiability algorithm is used to generate fault test vectors to be injected. The experimental results show that compared with the full scan, the proposed method reduces the number of scanning flip-flops by 28. 04% on average, which reduces the logic overhead in the hardware emulation of fault injection attack at the cost of adding a small number of input ports.